View LTC7003_9002136.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/LTC7003 typical application features description fast 60v protected high side nmos static switch driver the lt c ? 7003 is a fast high side n-channel mosfet gate driver that operates from input voltages up to 60v. it contains an internal charge pump that fully enhances an external n-channel mosfet switch, allowing it to remain on indefinitely. its powerful driver can easily drive large gate capacitances with very short transition times, making it well suited for both high frequency switching applications or static switch applications that require a fast turn-on and/or turn-off time. when an internal comparator senses that the switch current has exceeded a preset level, a fault flag is asserted and the switch is turned off after a period of time set by an external timing capacitor. after a cooldown period, the LTC7003 automatically retries. the LTC7003 is available in the thermally-enhanced 16-lead msop package. high side switch with 100% duty cycle and overcurrent protection turn-on transient waveform n wide operating v in : 3.5v to 60v n 1 pull-down, 2.2 pull-up for fast turn-on and turn-off times with 35ns propagation delays n internal charge pump for 100% duty cycle n short-circuit protected n adjustable current trip threshold n current monitor output n automatic restart timer n open-drain fault flag n adjustable turn-on slew rate n gate driver supply from 3.5v to 15v n adjustable v in undervoltage and overvoltage lockouts n adjustable driver supply v cc undervoltage lockout n low shutdown current: 1a n cmos compatible input n thermally enhanced, high voltage capable 16-lead msop package applications n static switch driver n load and supply switch driver n electronic valve driver n high frequency high side gate driver l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. lt c7003 7003f 0.1f 100k 1nf 0.007 v in 3.5v to 60v load 3.5v to 60v 3a continous max 7003 ta01a v in = 60v v in v cc fault timer inp sns + sns ? bst tgup tgdn 20ns/div ts LTC7003 v ccuv ovlo gnd run pins not used in this circuit: imon iset off on v inp 2v/div v load 20v/div 7003 ta01b 1f
2 for more information www.linear.com/LTC7003 pin configuration absolute maximum ratings supply voltages v in .......................................................... C 0.3 v to 65v b st-ts ..................................................... C 0. 3v to 15v v cc ...........................................................C 0.3v to 15v bs t voltage ............................................ C 0. 3v to 80v ts voltage ..................................................... C 6v to 65v run, sns + and sns C voltages .................. C 0.3 v to 65v sns + C sns C ......................................... C 0.3 v to + 0.3v inp voltage .................................................... C 6v to 15v driver outputs tgup, tgdn ................................ ( note 7) timer, fa u lt , voltages ............................... C 0. 3v to 15v v ccuv , i set , i mon , ovlo voltages ................. C 0.3 v to 6v operating junction temperature range (notes 2, 3, 4) lt c70 03 e, lt c7003 i .......................... C 40 c to 125 c lt c70 03 h ........................................... C 40 c to 150 c lt c70 03 mp ........................................ C 55 c to 150 c storage temperature range ................... C 65 c to 150 c lead temperature (soldering, 10 sec) ms op package .................................................. 30 0 c (note 1) order information lead free finish tape and reel part marking* package description temperature range LTC7003emse#pbf LTC7003emse#trpbf 7003 16-lead plastic msop C40c to 125c LTC7003imse#pbf LTC7003imse#trpbf 7003 16-lead plastic msop C40c to 125c LTC7003hmse#pbf LTC7003hmse#trpbf 7003 16-lead plastic msop C40c to 150c LTC7003mpmse#pbf LTC7003mpmse#trpbf 7003 16-lead plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *temperature grades are identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. LTC7003 1 2 3 4 5 6 7 8 run v in v cc v ccuv fault timer inp ovlo 17 gnd 16 15 14 13 12 11 10 9 sns + sns ? bst ts tgup tgdn i mon i set top view mse package 16-lead plastic msop (note 6) t jmax = 150c, ja = 45c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb http://www.linear.com/product/LTC7003#orderinfo lt c7003 7003f
3 for more information www.linear.com/LTC7003 electrical characteristics symbol parameter conditions min typ max units input supplies v in input voltage operating range 3.5 60 v ts operating voltage range 0 60 v sns+/C input voltage range independent of v in 3.5 60 v total supply current (note 8) on mode sleep mode shutdown mode c vcc ?=?1f, v bst-ts = 13v, v inp ?=?4v, v run = 2v v inp ?=?0.4v, v run = 2v v run ?=?0v l l 60 37 1 85 60 3 a a a v in dc supply current (note 5) on mode sleep mode shutdown mode c vcc ?=?1f, v bst-ts = 13v, v inp ?=?4v, v run = 2v v inp ?=?0.4v, v run = 2v v run ?=?0v 35 25 1 a a a sns + current v inp ?=?4v, v run = 2v v inp ?=?0.4v, v run = 2v v run ?=?0v 21 12 0 a a a sns C current v inp ?=?4v, v run = 2v v inp ?=?0.4v, v run = 2v v run = 0v 4 0 0 6 a a a v cc ldo output voltage c vcc ?=?1f, v in = 12v 10 v v cc ldo dropout voltage (v in -v cc ) v in = 6v, i vcc = C1ma 0.2 v v cc uvlo v cc undervoltage lockout v ccuv = open, v in ?=?v cc v cc rising v cc falling hysteresis v ccuv = 0v, v in ?=?v cc v cc rising v cc falling hysteresis v ccuv = 1.5v, v in ?=?v cc v cc rising v cc falling hysteresis l l l l 6.5 5.8 3.1 2.8 9.7 9.1 7.0 6.4 600 3.5 3.2 300 10.5 9.9 600 7.5 6.9 3.7 3.4 10.9 10.3 v v mv v v mv v v mv bootstrapped supply (bst -ts) v bst-ts v tg above v ts with inp?=?3v (dc) v in ?=?v cc ?=?v ts ?=?7v, i bst ?=?0a v in ?=?v cc ?=?v ts ?=?10v, i bst ?=?0a v in ?=?v ts ?=?60v, i bst ?=?0a l l 9 10 10 11 12 12 14 14 14 v v v charge pump output current v ts ?=?20v, v bst-ts ?=?10v l C15 C30 a bst-ts floating uvlo bst-ts rising bst-ts falling 3.1 2.8 v v output gate driver (tg) tg pull-up resistance v in ?=?v bst ?=?12v, v vccuv ?=?0v l 2.2 7 tg pull-down resistance v in ?=?v bst ?=?12v, v vccuv ?=?0v l 1 4 t r output rise time 10% to 90%, cl?=?1nf 10% to 90%, cl?=?10nf 13 90 ns ns t f output fall time 10% to 90%, cl?=?1nf 10% to 90%, cl?=?10nf 13 40 ns ns t plh t phl input to output propagation delay v inp rising, cl?=?1nf v inp falling, cl?=?1nf l l 35 35 70 70 ns ns the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in ?=?v sns +?=?10v, v cc ?=?v bst ?=?10v, v ts ?=?gnd?=?0v, unless otherwise noted. lt c7003 7003f
4 for more information www.linear.com/LTC7003 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC7003 is tested under pulsed load conditions such that t j ??t a . the LTC7003e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7003i is guaranteed over the C40c to 125c operating junction temperature range, the LTC7003h is guaranteed over the C40c to 150c operating junction temperature range and the LTC7003mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes ; operating lifetime is derated for junction temperatures greater than 125 c . note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja is 45c / w. note 4: this ic includes over temperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: for application concerned with pin creepage and clearance distances at high voltages, the mse16(12) variation package should be used. see applications information. note 7: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only; otherwise permanent damage may occur. note 8: total supply current is the sum of the current into the v in , sns + and sns C pins. electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in ?=?v sns +?=?10v, v cc ?=?v bst ?=?10v, v ts ?=?gnd?=?0v, unless otherwise noted. symbol parameter conditions min typ max units operation v ih v il input threshold voltages v inp rising v inp falling hysteresis l l 1.7 1.3 2 1.6 400 2.2 1.8 v v mv input pull-down resistance v inp ?=?1v 1 m run and ovlo pin threshold voltages rising falling hysteresis 1.16 1.05 1.21 1.10 110 1.26 1.15 v v mv run and ovlo leakage current v run = 1.3v, v ovlo = 1.3v l C100 0 100 na timer threshold voltage v timer rising to v fault going low 1.25 1.3 1.35 v timer early warning voltage v fault going low to (tg-ts) going low 75 100 125 mv timer pin fault pull-up current v timer ?=?1.0v, i set ?=?open l C115 C100 C80 a timer pin pull-down current v timer ?=?0.6v i set ?=?open v sns ?=?0mv l 2.0 2.5 3.0 a fault output low voltage i fault ?=?1ma l 0.2 0.5 v fault leakage current v fault ?=?5v l C100 0 100 na v th current sense threshold voltage v sns = (v sns + C v sns C) i set ?=?open v iset ?=?1.2v v iset ?=?0v l 22 54 15 30 60 20 36 64 24 mv d retry duty cycle v sns = 200mv c timer = 1nf l 0.06 0.1 % i set and v ccuv pull-up current v iset ?=?1.0v, v ccuv = 1.0v C11.3 C10 C8.7 a i mon output voltage v sns ?=?60mv, v timer ?=?0v, v inp = 3.5v v sns ?=?30mv, v timer ?=?0v, v inp = 3.5v l 1.12 1.2 0.6 1.28 v v over -current to tg low propagation delay v sns step 10mv to 50mv, i set ?=?open, v timer ?=?v cc , v inp = 3.5v 70 ns lt c7003 7003f
5 for more information www.linear.com/LTC7003 typical performance characteristics total supply current vs v in voltage driver on resistance vs v bst-ts voltage charge pump no-load output voltage vs v ts charge pump load regulation charge pump output current vs v ts ?v th vs temperature run and ovlo threshold voltages vs temperature v ccuv lockout vs temperature driver on resistance vs temperature t a = 25c, unless otherwise noted. lt c7003 7003f 0 ?5.0 5.0 i bst (a) 7003 g05 i set = 0v i set = open i set = 1.2v i set = 1.5v temperature (c) ?50 15 0 50 100 150 0 10 20 30 40 50 30 60 70 80 threshold voltage (mv) current sense 7003 g06 rising falling temperature (c) ?50 45 0 50 100 150 1.05 1.10 1.15 1.20 1.25 threshold voltage (v) 60 7003 g07 v ccuv = open rising falling temperature (c) ?50 0 50 100 150 0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 v ccuv lockout (v) 7003 g08 v 20.0 bst?ts = 12v tgup tgdn temperature (c) ?50 0 50 100 150 40.0 0 1 2 3 4 resistance () 7003 g09 60.0 80.0 v bst?ts = 13v 100.0 total supply current (a) 7003 g01 i bst = 0a v cc = 4v v cc = 5v v cc = 6v v cc = 7v v cc 8v v ts (v) v sns + =v in 0 5 10 15 20 0 2 4 6 8 v ccuv =open 10 12 14 v bst - v ts (v) 7003 g03 v ccuv = 0v tgup tgdn v bst-ts (v) 3 v ccuv = 0v 6 9 12 15 0 1 2 3 4 5 shutdown 6 r dson () 7003 g02 v cc = 4v v ts = 4v v ts = 6v v ts = 8v v ts = 10v v ts = 12v i bst (a) sleep 0 ?20 ?40 ?60 ?80 ?1 1 3 5 7 on 9 11 13 15 v bst -v ts (v) 7003 g04 v cc = 7v v bst?ts = 10v 25c 150c v in voltage (v) v ts (v) 0 15 30 45 60 ?45.0 ?35.0 ?25.0 ?15.0
6 for more information www.linear.com/LTC7003 typical performance characteristics v in supply current vs temperature sns + supply current vs temperature sns C supply current vs temperature input threshold voltage vs temperature sns + fault threshold vs temperature overcurrent to tgdn?=?low delay time vs temperature retry duty cycle vs temperature v bst-ts floating uvlo voltage vs temperature i set and v ccuv pull-up current vs temperature v in = 10v v in = v sns + = v sns ? = 10v v in = v sns + = v sns ? = 10v v iset = 1.0v v vccuv = 1.0v t a = 25c, unless otherwise noted. lt c7003 7003f 10 50 100 150 0.060 0.065 0.070 0.075 0.080 duty cycle (%) 7003 g16 15 rising falling temperature (c) ?50 0 50 100 150 2.0 2.5 20 3.0 3.5 4.0 threshold voltage (v) 7003 g17 temperature (c) ?50 0 50 100 25 150 ?11.0 ?10.5 ?10.0 ?9.5 ?9.0 pull?up current (a) 7003 g18 30 35 40 7003 g10 shutdown sleep on current (a) temperature (c) temperature (c) ?50 0 50 100 150 ?10 0 10 20 ?50 30 current (a) 7003 g11 shutdown sleep on shutdown, sleep on temperature (c) ?50 0 50 0 100 150 ?2.0 0 2.0 4.0 6.0 7003 g12 current (a) v in = 10v 50 rising falling temperature (c) ?50 0 50 100 150 0 0.5 100 1.0 1.5 2.0 2.5 3.0 threshold voltage (v) 7003 g13 rising falling temperature (c) 150 ?50 0 50 100 150 3.0 3.1 3.2 3.3 3.4 0 threshold voltage (v) 7003 g15 c timer = 1nf temperature (c) ?50 0 50 100 150 18 5 19 20 21 22 time (s) 7003 g15 c timer = 1nf temperature (c) ?50 0
7 for more information www.linear.com/LTC7003 pin functions run (pin 1): run control input. a voltage on this pin above 1.2v enables normal operation. forcing this pin below 0.7v shuts down the LTC7003, reducing quiescent current to approximately 1a. optionally connect to the input supply through a resistive divider to set the under - voltage lockout. v in (pin 2): main supply pin. a bypass capacitor with a minimum value of 0.1f should be tied between this pin and gnd. v cc (pin 3): output of internal ldo and power supply for gate drivers and internal circuitry. decouple this pin to gnd with a minimum 1.0f low esr ceramic capacitor. do not use the v cc pin for any other purpose. v cc can be overdriven from an external high efficiency source for high frequency switching applications that require higher power delivered to the external mosfet. do not connect v cc to a voltage greater than v in . v ccuv (pin 4): v cc supply undervoltage lockout. a resistor on this pin sets the reference for the gate drive undervoltage lockout. the voltage on this pin in the range of 0.4v to 1.5v is multiplied by 7 to be the undervoltage lockout for the gate drive (v cc pin). short to ground to set the minimum gate drive uvlo of 3.5v. leave open to set gate drive uvlo to 7.0v fault (pin 5): open drain fault output. this pin pulls low after the voltage on the timer pin has reached the fault threshold of 1.3v. it indicates the pass transistor is about to turn off due to an overcurrent condition. the typical pull-down impedance is 200. the fault pin does not go to a high-impedance state until the overcurrent condition and the timer cooldown period expire. if the timer pin is pulled above 3.5v, the timer function is disabled. in this state this pin pulls low when the v tgup-ts signal is driven high. timer (pin 6) : fault timer input. a timing capacitor, ct, from the timer pin to gnd sets the times for fault warning, fault turn off and retry periods (see applications information). when the timer pin is connected to a voltage higher than 3.5v , an overcurrent condition will immediately pull the tgup pin to ts. tgdn will not go high again until the fault condition is reset by the inp pin going low and then back high. inp (pin 7): input signal. cmos compatible input ref - erence to gnd that sets the state of tgdn and tgup pins (see applications information). inp has an internal 1m pull-down to gnd to keep tgdn pulled to ts during startup transients. ovlo (pin 8): overvoltage lockout input. connect to the input supply through a resistor divider to set the overvolt - age lockout level. a voltage on this pin above 1.21v causes tgdn to be pulled to ts. normal operation resumes when the voltage on this pin decreases below 1.11v . triggering an ovlo causes a fault condition. ovlo should be tied to gnd when not used. i set (pin 9): current trip threshold set. a resistor on this pin to gnd sets the peak current threshold. the voltage on this pin (internally clamped between 0.4v and 1.5v) is divided by 20 to be the current comparator reference. short to gnd from minimum peak current (20mv v th ). leave open for an accurate peak current (30mv v th ). i mon (pin 10): current monitor. the voltage on this pin with respect to gnd represents the voltage across the sense resistor multiplied by 20. the range on this pin is 0v to 1.5v. tgdn (pin 11): high current gate driver pull-down. this pin pulls down to ts. for the fastest turn-off, tie this pin directly to the gate of the external high side mosfet. tgup (pin 12): high current gate driver pull-up. this pin pulls up to bst. tie this pin to tgdn for maximum gate drive transition speed. a resistor can be connected between this pin and the gate of the external mosfet to control the in-rush current during turn-on. see applications information. ts (pin 13): top (high side) source connection or gnd if used in ground referenced applications. bst (pin 14): high side bootstrapped supply. an external capacitor with a minimum value of 0.1f should be tied between this pin and ts. voltage swing on this pin is 12v to (v in ?+?12v). lt c7003 7003f
8 for more information www.linear.com/LTC7003 pin functions block diagram 1.0v 20mv to 75mv 7003 bd load c t + ? + ? + ? + ? + ? + ? + ? + ? 200 2.3v 2.3v 9r r 3.5v 1.4v 1.3v 0.4v 10a 2.3v 100k 10a 1m cv cc c bst m1 pch nch /20 3.5v to 60v 20x v cc d1 (optional) sns C (pin 15), sns + (pin 16) : current sense comparator input. place a sense resistor in series with the drain of the external mosfet to set the peak current. the sns C pin is connected to the drain side of the sense resistor. use a kelvin connection from the sns + and sns C pins to the sense resistor. the current comparator trip threshold voltage, v th is the i set voltage divided by 20. the trip threshold is internally clamped to a minimum of 20mv and a maximum of 75mv. if i set is open or greater than 2.0v , v th is set internally to 30mv. gnd (exposed pad pin 17): ground. the exposed paddle must be soldered to the pcb for rated electrical and ther - mal performance. lt c7003 7003f 1.21v logic level shift up level shift down charge pump 102.5a/5a 2.5a 16 15 12 14 11 13 6 5 sns + sns + 3.5v sns ? bst tgup ts tgdn fault timer 2 9 10 3 v cc 1 8 7 4 run v ccuv ovlo inp v in i set i mon r sns
9 for more information www.linear.com/LTC7003 operation the LTC7003 is designed to receive a ground-referenced, low voltage digital input signal, inp and quickly drive and protect a high side n-channel power mosfet whose drain can be up to 60v above ground. the LTC7003 is capable of driving a 1nf load using a 12v bootstrapped supply voltage (v bst Cv ts ) with 35ns of propagation delay and fast rise/fall times. the high gate drive voltage reduces external power losses associated with external mosfet on-resistance. the strong drivers not only provide fast turn on and off times but hold the tgup and tgdn to ts voltages in the desired state in the presence of high slew rate transients which can occur driving inductive loads at high voltages. overcurrent protection the lt c7003 protects a high side n-channel mosfet from an overcurrent condition by monitoring the voltage across an external sense resistor placed in series with the drain of an external mosfet and forcing the external mosfet to turn off by pulling tgdn to ts when the voltage across the sense resistor, v sns , exceeds the current comparator threshold voltage, v th , after a period of time set by the timing capacitor, c t . when an overcurrent condition is detected with i set open, v th is internally programmed to a low value of 30mv minimizing the external conduction loss associated with current sensing by allowing the use of lower value sense resistors. a resistor placed between i set and ground allows v th to be programmed from 20mv to 75mv . an adjustable fault and overcurrent timer is enabled by placing a capacitor, c t from the timer pin to ground and allows the load to continue functioning during brief overcurrent transient events while protecting the mosfet from long periods of high currents. an external fault flag is available which can warn of an impending mosfet turn off. a fast turn-off mode where tgdn is immediately pulled to ts due to an overcurrent is available by connecting the timer pin to v cc . current monitor the LTC7003 provides an output voltage referenced to ground on the i mon pin that reflects the current flowing through the external sense resistor connected between sns + and sns C while tgup is high. the voltage on i mon is the voltage difference between the sns + and sns C pins multiplied by 20x and referenced to ground with a range of 0v to 1.5v. the i mon output voltage has an output impedance of 100k and is pulled to ground with a 100k resistor when inp is low. v cc power power for the mosfet driver and internal circuitry is derived from the v cc pin. the v cc pin voltage is gener - ated from an internal p-channel ldo connected to v in . v cc can also be overdriven from a high efficiency exter - nal source for high frequency switching applications that require higher power delivered to external mosfet. v cc should never be driven higher than v in or permanent damage to the lt c7003 could occur. (refer to block diagram) timing diagram 7003 td lt c7003 7003f 10% v ih v il input (inp) output (tg-ts) input rise/fall time < 10ns t plh t r t phl t f 90%
10 for more information www.linear.com/LTC7003 operation internal charge pump the LTC7003 contains an internal charge pump that enables the mosfet gate drive to have 100% duty cycle. the charge pump regulates the bst-ts voltage to 12v reducing external power losses associated with external mosfet on-resistance. the charge pump uses the higher voltage of ts or v cc as the source for the charge. start-up and shutdown if the voltage on the run pin is less than 0.7v , the LTC7003 enters a shutdown mode in which all internal circuitry is disabled, reducing the dc supply current to approximately 1a. when the voltage on the run pin exceeds 0.7v, the internal ldo connected to v in is enabled and regulates v cc to 10v. at v in voltages less than 10v, the ldo will operate in drop-out and v cc will follow v in . when the volt - age on the run pin exceeds 1.21v , the input circuitry is enabled allowing tgup and tgdn to be driven high with respect to ts. protection circuitry when using the LTC7003 , care must be taken not to exceed any of the ratings specified in the absolute maximum ratings section. as an added safeguard, the LTC7003 incorporates an overtemperature shutdown feature. if the junction temperature reaches approximately 180c, the LTC7003 will enter thermal shutdown mode and tgdn will be pulled to ts. after the part has cooled below 160c , tgdn will be allowed to go back high. the over - temperature level is not production tested. the LTC7003 is guaranteed to start a temperatures below 150c. the LTC7003 additionally implements protection features which prohibit tgup being pulled to bst when v in , v cc or (v bst Cv ts ) are not within proper operating ranges. by using a resistive divider from v in to ground, the run and ovlo pins can serve as a precise input supply overvolt - age/undervoltage lockouts. tgdn is pulled to ts when either run falls below 1.11v or ovlo rises above 1.21v, which can be configured to limit switching to a specific range on input supply voltages. furthermore, if v in falls below 3.5v , an internal undervoltage detector pulls tgdn to ts. v cc contains an undervoltage lockout feature that will pull tgdn to ts and is configured by the v ccuv pin. if v ccuv is open, tgdn is pulled to ts until v cc is greater than 7.0v . by using a resistor from v ccuv to ground, the rising undervoltage lockout on v cc can be adjusted from 3.5v to 10.5v. an additional internal undervoltage lockout is included that will pull tgdn to ts when the floating voltage from bst to ts is less than 3.1v (typical). (refer to block diagram) lt c7003 7003f
11 for more information www.linear.com/LTC7003 applications information input stage the LTC7003 employs cmos compatible input thresholds that allow a low voltage digital signal connected to inp to drive standard power mosfets. the LTC7003 contains an internal voltage regulator which biases the input buffer connected to inp allowing the input thresholds (v ih ?=?2.0v , v il ?=?1.6v ) to be independent of variations in v cc . the 400mv hysteresis between v ih and v il eliminates false triggering due to noise events. however, care should be taken to keep inp from any noise pickup, especially in high frequency, high voltage applications. inp also contains an internal 1m pull-down resistor to ground, keeping tgdn pulled to ts during startup and other unknown transient events. during shutdown (v run <0.7v) the internal 1m pull-down resistor is dis - abled and inp becomes high impedance. inp has an absolute maximum of C 6v to +15v which allows the signal driving inp to have voltage excursions outside the normal power supply and ground range. it is not uncommon for signals routed with long pcb traces and driven with fast rise/fall times to inductively ring to voltages higher than power supply or lower than ground. output stage a simplified version of the LTC7003 output stage is shown in figure?1. the pull-down device is an n-channel mosfet with a typical 1 r ds(on) and the pull-up device is a p-channel mosfet with a typical 2.2 r ds(on) . the pull-up and pull-down pins have been separated to allow the turn-on transient to be controlled while maintaining a fast turn-off. the LTC7003 powerful output stage ( 1 pull-up and 2.2 pull-down) minimizes transition losses when driv - ing external mosfets and keeps the mosfet in the state commanded by inp even if high voltage and high fre - quency transients couple from the power mosfet back to the driving circuitry. the large gate drive voltage on tgup and tgdn reduces conduction losses in the external mosfet because r ds(on) is inversely proportional to its gate overdrive (v gs ?C?v th ). sns + and sns C pins sns + and sns C are the inputs to the high side current comparator and current monitor. the common mode operational voltage range for these pins is 3.5v to 60v independent of any other voltages. sns + also provides power to the current comparator and current monitor and draws approximately 21a when not shut down and inp is high. sns C draws a bias current of approximately 4a when not shut down and inp is high. when sns + is less than 3.2v , a fault condition occurs and the adjustable fault timer is enabled with the same behavior as an overcurrent fault. normally the sns pins are connected to the drain side of the external mosfet. however, the sns pins can be connected to the source side of the external mosfet as long as the source voltage rises above 3.5v before the fault timer expires. see fault timer and fault flag section. i set pin the current comparator has an adjustable threshold voltage, v th , of 20mv to 75mv and is set by placing a resistor to ground on the i set pin. the i set pin is biased with an internal 10a current source. floating i set enables the current comparator to have an accurate 30mv threshold voltage which allows for lower value sense resistors and reduces the external power dissipation. by placing a 40k to 150k resistor between i set and ground, the sense threshold voltage can be programmed figure?1. simplified output stage 12v 7003 f01 + ? + ? 2.2 1 high speed 60v level shifter charge pump a v = 1 lt c7003 7003f bst tgup tgdn ts v cc inp 30a LTC7003
12 for more information www.linear.com/LTC7003 applications information to values between 20mv and 75mv. the value of resistor for a particular sense threshold voltage can be selected using figure?2 or the following equation: r iset = ? v th 0.5a where 20mv< v th < 75mv. figure?2. r iset selection optional filtering can be placed in series with the sns C pin as shown in figure?3. note that the sns C pin takes 4a of bias current which will affect the current sense and current monitoring functions. the value of r f lt needs to be less than 250 to keep current sensing error less than 1mv due to the bias current associated with sns C pin. sns + sns ? tgup tgdn ts 7003 f03 inp = lo, 0a inp = hi, 4a r f lt c f lt r sns m1 power load figure?3. sense pins filtering fault timer and fault flag the lt c7003 includes an adjustable fault timer. connecting a capacitor from the timer pin to ground sets the delay period before the external mosfet is turned off during an overcurrent fault condition. the same capacitor also sets the cooldown period before the external mosfet is allowed to turn back on. once a fault condition is detected, a 100a current charges the timer pin. when the voltage on the timer pin reaches 1.3v , the fa u lt pin pulls low to indicate the detection of a fault condition and provide warning of an impending power loss. after the timer voltage crosses the 1.4v threshold, tgdn is immediately pulled to ts turning off the external mosfet. the on- time of the external mosfet, t over_current , during an overcurrent event is given by the following equation: t over _current = 1.4v c timer 100a the warning time, t warning , generated by an overcurrent event is given by the following equation: t warning = 0.1v c timer 100a if the overcurrent fault condition disappears before timer has reached 1.4v , timer is discharged by a 2.5a current. if timer had reached 1.3v ( fa u lt has gone low) and the overcurrent fault condition disappears, timer is discharged with a 2.5a current and fa u lt will be reset when timer reaches 0.4v . the on-time and warning times are shown graphically in figure?4. time v tmr (v) 7003 f04 t over_current 14ms/f t warning 1ms/f t fault 13ms/f 1.4 1.3 figure?4. fault timer trip points lt c7003 7003f 210 240 0 10 20 30 40 50 60 70 i set resistor to ground (k) 80 current sense threshold ?v th (mv) 7003 f02 LTC7003 0 30 60 90 120 150 180
13 for more information www.linear.com/LTC7003 applications information cooldown period and restart as soon as timer reaches 1.4v , tgdn is pulled to ts in an overcurrent fault condition and the timer pin starts dis - charging with a 2.5a c u rrent. when timer reaches 0.4v , timer charges with a 2.5a current. when timer reaches 1.4v , it starts discharging again with a 2.5a current. this pattern repeats 32 times to form a long cooldown timer period ( t cool_down ) before retry (figure?5). if inp is cycled low, tgdn will be pulled to ts and timer will be pulled low with an internal 100k resistor. if inp is cycled low during the cooldown period, the timer counter will be reset. if inp then goes high, tgup will pulled to bst and the fault timer will be reactivated with the timer voltage starting from its current value. at the end of the cooldown period (when timer drops below 0.4v for the 32nd time), the LTC7003 retries, pull - ing tgup to bst and turning on the external mosfet. the fault pin will then go to a high impedance state. the total cooldown timer period is given by: t cool _down = 63 1.0v c timer 2.5a the retry duty cycle in percent is to a first order indepen - dent of c t and is defined by: d = 100 t over _current t over _current + t cool _down to defeat the automatic retry, place a 100k resistor in parallel with the timer capacitor. note that the time to turn off from an overcurrent fault will be increased by 7% and the fault pin will remain low indicating a fault has occurred. to get the LTC7003 to retry and to clear the fault flag the inp signal needs to cycle low then back high. typical turn-off times and cooldown periods for some standard value timer capacitors are shown table?1: table?1. fault time for typical capacitors c timer (nf) t over_current (s) t cool_down (s) retry duty cycle % <0.1 1.4 0.0005 0.28 1 14 0.025 0.06 10 140 0.250 0.06 100 1400 2.500 0.06 cooldown period (t cool_down ) 7003 f05 timer ?v sns v (tg-ts) (tgup shorted to tgdn) fault >30mv <30mv 0.4v 1 st 2 nd 31 st 32 nd inp 1.30v 1.40v figure?5. auto retry cool-down timer cycle lt c7003 7003f
14 for more information www.linear.com/LTC7003 applications information 7003 f06 timer ?v sns v (tg-ts) (tgup shorted to tgdn) fault >30mv >30mv <30mv 0.4v 1 st 1 st 31 st 32 nd inp 1.30v 1.40v figure?6. auto retry with inp cycling low fast turn-off mode if the timer pin is connected to v cc or any other supply greater than 3.5v (abs max 15v ), an overcurrent event will immediately pull tgdn to ts and the LTC7003 will remain there until the inp signal has cycled low and then back high. in fast turn-off mode, the typical delay from a v sns overcurrent step to tg going low is around 70ns, so very fast short-circuit events can be detected. also, when the timer pin is connected to a voltage greater than 3.5v , the fault signal is redefined to be the inverse state of the high side pull-up (v tgup ?C ?v ts ). the fault signal can be used in this application as low-voltage digital information that has been level shifted down from the high side mosfet. an application for this could include using this signal to wait until v tgup Cv ts has gone low before turning on a redundant power mosfet. high side current monitor output the LTC7003 contains a high side current monitor output. the high side differential voltage sensed across the sns + and sns C pins (v sns ) is multiplied by 20 and ground referenced on the i mon pin which makes it suitable for monitoring and regulating the mosfet current. the work - ing range of i mon is 0v to 1.5v as v sns varies from 0mv to 75mv . the i mon pin is a voltage output whose nominal output impedance is 100k and should not be resistively loaded. the current monitor output is only available if the inp signal is high, otherwise the i mon pin is pulled to ground. a block diagram of the i mon circuit is shown in figure?7. the gm of the transimpedance amplifier tracks the 100k internal resistor to ground which makes varia - tions over process minimal. i mon g m = 200a/v 7003 f07 sns + sns ? + ? 100k inp figure?7. i mon block diagram run pin and external input overvoltage/undervoltage lockout the run pin has two different threshold voltage levels. pulling run below 0.7v puts the LTC7003 into a low quiescent current shutdown mode (i q? ~? 1a ). when the run pin is greater than 1.20v, the part is enabled. figure?8 shows examples of configurations for driving the run pin from logic. lt c7003 7003f LTC7003
15 for more information www.linear.com/LTC7003 applications information the run and ovlo pins can alternatively be configured as precise undervoltage (uvlo) and overvoltage (ovlo) lockouts on the v in supply with a resistive divider from v in to ground. a simple resistive divider can be used as shown in figure?9 to meet specific v in voltage requirements. when run or ovlo is greater than 1.2v , tgdn will be pulled to ts and the external mosfet will be turned off. supply v in r1 m2 7003 f08 run run figure?8. run pin interface to logic d5 7003 f09 v in r4 r3 r5 ovlo run figure?9. adjustable uv and ov lockout the current that flows through the r3?C?r4?C?r5 divider will directly add to the shutdown, sleep and active current of the LTC7003 , and care should be taken to minimize the impact of this current on the overall current used by the application circuit. resistor values in the megaohm range may be required to keep the impact of the quiescent shutdown and sleep currents low. to pick resistor values, the sum total of r3 ?+?r4 ?+?r5 (r total ) should be chosen first based on the allowable dc current that can be drawn from v in . the individual values of r3, r4 and r5 can then be calculated from the following equations: r5 = r total 1.21v rising v in ovlo threshold r4 = r total 1.21v rising v in uvlo threshold ? r5 r3 = r total ? r5 ? r4 for applications that do not need a precise external ovlo the ovlo pin is required to be tied directly to ground. the run pin in this type of application can be used as an external uvlo using the above equations with r5?=?0. similarly, for applications that do not require a precise uvlo, the run pin can be tied to v in . in this configura - tion, the uvlo threshold is limited by the internal v in uvlo thresholds as shown in the electrical characteristics table. the resistor values for the ovlo can be computed using the above equations with r3?=?0. be aware that the ovlo pin cannot be allowed to exceed its absolute maximum rating of 6v . to keep the voltage on the ovlo pin from exceeding 6v , the following relationship should be satisfied: v in(max) r5 r3 + r4 + r5 ? ? ? ? ? ? < 6v if the v in(max) relationship for the ovlo pin cannot be satisfied, an external 5v zener diode should also be placed from ovlo to ground in addition to any lockout setting resistors. bootstrapped supply (bst-ts) an external bootstrapped capacitor, c b , connected between bst and ts supplies the gate drive voltage for the mosfet driver. the LTC7003 keeps the bst-ts supply charged with an internal charge pump, allowing for duty cycles up to 100%. when the high side external mosfet is to be turned on, the driver places the c b volt- age across the gate-source of the mosfet. this enhances the high side mosfet and turns it on. the source of the mosfet, ts, rises to v in and the bst pin follows. with the high side mosfet on, the bst voltage is above the input supply; v bst ?= ?v in ?+?12v . the boost capacitor, c b , supplies the charge to turn on the external mosfet and needs to have at least 10 times the charge to turn on the external mosfet fully. the charge to turn on the external mosfet is referred to gate charge, q g , and is typically specified in the external mosfet data sheet. gate charge can range from 5nc to hundreds of ncs and is influenced by the gate drive level and the type of external mosfet used. for most applications, a capacitor value of 0.1f for lt c7003 7003f LTC7003 LTC7003 LTC7003
16 for more information www.linear.com/LTC7003 applications information c b will be sufficient. however, the following relationship for c b should be maintained: c b > 10 external mosfet q g 1v the internal charge pump that charges the bst-ts supply outputs approximately 30a to the bst pin. if the time to charge the external bootstrapped capacitor, c b from initial power-up with the internal charge pump is not suf - ficient for the application, a low reverse leakage external silicon diode, d1 , with a reverse voltage rating greater than v in connected between v cc and bst should be used as shown in figure?10. an external silicon diode between v cc and bst should be used if the following relationship cannot be met: bst diode required if power-up to inp going high < c bst 12v 30a ? 40ms figure?10. external bst diode 7003 f10 d1 c b bst ts v cc another reason to use an external silicon diode between v cc and bst is if the external mosfet is switched at a frequency so high that the bst-ts supply collapses. an external silicon diode between v cc and bst should be used if the following relationship cannot be met: bst diode required if switching frequency > 30a 2 mosfet q g ? 500hz a schottky diode should not be used between v cc and bst, as the reverse leakage of the schottky diode at hot will be more current than the charge pump can overcome. some example silicon diodes with low leakage include: ? ba s116 series, multiple vendors ? ba s416, nexperia ? ba q34, vishay semiconductors ? cmo d6001, central semiconductor v cc generation the v cc pin provides the power for the mosfet gate drivers and internal circuitry. the LTC7003 features an internal p-channel low dropout regulator (ldo) that can supply power at v cc from the v in supply pin or v cc can be driven from an external power supply. if the internal p-channel ldo is used to power v cc , it must have a mini - mum 1.0f low esr ceramic capacitor to ensure stability and should not be connected to any other circuitry other than optionally biasing some pins on the LTC7003 ( fault , inp or timer). if the internal p-channel ldo is used to power v cc and an external silicon diode is used between v cc and bst, care must be taken not to switch an external mosfet at too high a frequency that can collapse the internal ldo. the internal ldo can only supply 1ma with a 200mv drop-out. in order to keep the internal ldo supply from collapsing when an external silicon diode is used from v cc to bst, the following relationship should be maintained: maximum switching frequency with internal ldo< 1ma 2 mosfet q g ? 20khz for higher gate charge applications, an external silicon diode between v cc and bst should be used and v cc can be driven from a high efficiency external supply. v cc should never be driven higher than v in or permanent damage to the LTC7003 could occur. v cc undervoltage comparator the LTC7003 contains an adjustable undervoltage lockout (uvlo) on the v cc voltage that pulls tgdn to ts and can be easily programmed using a resistor (r vccuv ) between the v ccuv pin and ground. the voltage generated on v ccuv by r vccuv and the internal 10a current source set the v cc uvlo. the rising v cc uvlo is internally limited within the range of 3.5v and 10.5v. if v ccuv is open the rising v cc uvlo is set internally to 7.0v. the value of resistor for a particular rising v cc uvlo can be selected using figure?11 or the following equation: r drvuv = rising v cc uvlo 70a where 3.5v < rising v cc uvlo < 10.5v. lt c7003 7003f LTC7003
17 for more information www.linear.com/LTC7003 applications information figure?11. v ccuv resistor selection mosfet selection the most important parameters in high voltage applica - tions for mosfet selection are the breakdown voltage bv dss , on-resistance r ds(on) and the safe operating area, soa. the mosfet, when off, will see the full input range of the input power supply plus any additional ringing than can occur when driving inductive loads. external conduction losses are minimized when using low r ds(on) mosfets. since many high voltage mosfets have higher threshold voltages (typical v th ?? 5v ) and r ds(on) is directly related to the (v gs C v th ) of the mosfet, the LTC7003 maximum gate drive of greater than 10v makes it an ideal solution to minimize external conduction losses associated with external high voltage mosfets. soa is specified in typical characteristic curves in power n-channel mosfet data sheets. the soa curves show the relationship between the voltages and current allowed in a timed operation of a power mosfet without causing damage to the mosfet. the overcurrent trip point (r sns and r iset ) of the LTC7003 and timer capacitor should be chosen to stay within the soa region of the mosfet selected for the application. limiting inrush current during turn-on driving large capacitive loads such as complex electrical systems with large bypass capacitors should be powered using the circuit shown in figure?12. the pull-up gate drive to the power mosfet from tgup is passed through an rc delay network, r g and c g , which greatly reduces the turn-on ramp rate of the mosfet. since the mosfet source voltage follows the gate voltage, the load is pow - ered smoothly from ground. this dramatically reduces the inrush current from the source supply and reduces the transient ramp rate of the load allowing for slower activation of sensitive electrical loads. the turn-off of the mosfet is not affected by the r c delay network as the pull-down for the mosfet gate is directly from the tgdn pin. note that the voltage rating on capacitor c g needs to be the same or higher than the external mosfet and c load . adding c g to the gate of the external mosfet can cause high frequency oscillation. a low power, low ohmic value resistor ( 10 ) should be placed in series with c g to dampen the oscillations as shown in figure?12 whenever c g is used in an application. alternatively, the low ohmic value resistor can be placed in series with the gate of the external mosfet. c b 1f c g 0.047f load 10 sns + sns ? r g 100k 7003 f12 r sns v in c load 100f tgup tgdn bst ts figure?12. powering large capacitive loads the values for r g and c g to limit the inrush current can be calculated from the below equation: i in_rush ? 0.7 12v c load r g c g lt c7003 7003f 150 180 210 240 0 1 2 3 4 5 rising v cc uvlo 6 7 8 9 10 11 v cc uvlo (v) 7003 f11 LTC7003 falling v cc uvlo v ccuv resistor to ground (k) 0 30 60 90 120
18 for more information www.linear.com/LTC7003 applications information for the values shown in figure?12 the inrush current will be : i in_rush ? 0.7 12v 100f 100k 0.047f ? 180ma correspondingly, the ramp rate at the load for the circuit in figure?12 is approximately: ? v load ? t ? 0.7 12v r g c g ? 2v/ ms when c g is added to the circuit in figure?12, the value of the bootstrap capacitor, c b , must be increased to be able to supply the charge to both to mosfet gate and capacitor c g . the relationship for c b that needs to be maintained when c g is used is given by: c b > 10 mosfet q g 1v + 10 c g optional schottky diode usage on ts when turning off a power mosfet that is connected to an inductive load (inductor, long wire or complex load), the ts pin can be pulled below ground until the current in the inductive load has completely discharged. the ts pin is tolerant of voltages down to C6v , however, an optional schottky diode with a voltage rating at least as high as the load voltage should be connected between ts and ground to prevent discharging the load through the ts pin of the LTC7003. see figure?13. l1 sns + sns ? tgup tgdn ts 7003 f13 r sns m1a v in load d2 figure?13. optional schottky diode usage reverse input protection to protect the load from discharging back into v in when the external mosfet is off and the v in voltage drops below the load voltage, two external n-channel mosfets should be used and must be configured in a back-to-back arrangement as shown in figure? 14. dual n-channel packages such as the following devices are good choices for space saving designs: ? fd s3 890 , fairchild/on semiconductor ? i rf 7380 pbf, infineon/ir ? sq jb 80ep, vishay/siliconix sns + sns ? tgup tgdn ts 7003 f14 r sns m1a m1b v in load figure?14. protecting load from voltage drops on v in design example as a design example, consider a fast power supply switch with the following specifications: v in ?= ?v load ?=? 4v to 60v, i load ?=? 3a, insertion loss < 0.5w at room temp with maximum load, output rise time with a 1f load is 1v/s (1a inrush current) and a shorted load should immedi - ately turn off the mosfet. the first item to select is the n-channel mosfet. the s i7812 dn is selected because it has sufficient breakdown voltage (bv dss_min ?=?75v ), sufficient continuous current rating for a 3a load (i d_max ?=? 5.7a ) and the on-resistance is low enough (r ds(on)_max ?=?46m ) to be able to meet the power loss specification. examining the mosfet data sheet, the v gs vs r ds(on) typical performance curve shows a sharp increase in r ds(on) as the mosfet v gs gets below 5.0v . since the default v cc uvlo is 7.0 v , the v ccuv pin can be left open. the ovlo pin is connected to ground since there is no specification for overvoltage lockout. lt c7003 7003f LTC7003 LTC7003 inp
19 for more information www.linear.com/LTC7003 applications information the value of the current sense resistor, r sns is calcu - lated next. with i set open, the LTC7003 has a fixed current sense threshold, v th , of 30mv typical and 22mv minimum. to provide a minimum 3a load current, the minimum specified v th ?=?22mv should be used for the r sns calculation below: r sns = 22mv 3a = 7.3m the closest standard value is 7m . the power dissipation of r sns is 63mw so choose a power rating of greater than 0.25w to provide adequate margin. the next item to check is to make sure the insertion loss specification is satisfied. the insertion loss is given by: p loss = i load 2 r ds(on)(max) + r sns ( ) = 3a 2 0.046 + 0.007 ( ) = 0.48w which meets the design specification of less than 0.5w. the fast output slew rate specification of 1v/s into a 1f load can be met by placing a resistor, r g , in series with the tgup pin to the mosfet gate, as well as connecting tgdn and a capacitor, c g , to ground on the mosfet gate. the values of r g and t g can be calculated from the following expression: r g c g ? 0.7 12v 1v / s = 8.4s c g needs to have a voltage rating as high as the bv dss of the mosfet. a good choice for c g is the avx 06031 c471 kat2a which has a value of 470pf and a volt - age rating of 100v . r g is then calculated to be 17. 8 k . the bootstrap capacitor c b can be calculated from the gate charge as specified in the mosfet data sheet and c g as follows: c b > 10 q g 1v + 10 c g = 10 24nc 1v + 10 470pf ? 0.33f to meet the short-circuit specification, the timer pin should be connected to v cc to enable immediate turn-off (approximately 70ns ) of the mosfet in the case of an overcurrent condition. if an overcurrent condition turns off the mosfet, it will not turn back on until the inp pin has cycled low then back high. the complete circuit is shown in figure?15. pc board layout considerations 1. solder the exposed pad on the backside of the LTC7003 packages directly to the ground plane of the board. 2. kelvin connect current sense resistor. 3. limit the resistance of the ts trace, by making it short and wide. 4. c b needs to be close to chip. 5. always include an option in the pc board layout to place a resistor in series with the gate of any external mosfet. high frequency oscillations are design depen - dent and having the option to add a series dampening resistor can save a design iteration of the pc board. figure?15. design example turn-on transient 0.33f 470pf 100v 1f 1f sns + sns ? v in v cc timer fault inp v ccuv 17.8k 7003 f15 0.007 si7812dn load 4v to 60v 3a continuous mode v in 4v to 60v gnd imon ovlo iset 10 tgup tgdn bst ts lt c7003 7003f 1a/div 7003 f15b LTC7003 v in = 60v 50s/div v inp 5v/div v load 30v/div id mosfet
20 for more information www.linear.com/LTC7003 typical applications protected redundant supply switchover with shoot through protection source side current sense load 10a continuous 1f ts bst ts bst v in run v in run fault v ccuv i mon i set 0.002 2 bsc057n08ns3g 0.002 2 bsc057n08ns3g 1nf 10k 10 10 sns + sns + sns ? sns ? tgdn tgdn tgup tgup 7003 ta03 v backup 7v to 60v main power 7v to 60v 100k 0.1f 0.1f 1nf 1f 1f 200k 6.98k gnd gnd v ccuv i mon i set v cc timer ovlo v cc inp timer ovlo inp fault note: the backup path will latch-off with an overcurrent fault. v main falling through 33v v main rising through 36v v load vs main power voltage v backup = 60v v backup = 60v 7003 ta02 note: with the sense resistor on the source side of the external mosfet, the load needs to rise higher than 3.5v within 140sec of inp going high or a fault will be indicated and the LTC7003 will retry. lt c7003 7003f 40 50 60 70 30 40 50 60 70 v load (v) LTC7003 7003 ta03b 40s/div v load 20v/div v tg?ts backup 10v/div v tg?ts main 10v/div LTC7003 7003 ta03c 2s/div v load 20v/div v tg?ts backup 10v/div v tg?ts main 10v/div v backup = 60v 7003 ta03d si7852adp 0.1f 1nf 1f 1f 0.02 100k 10nf v in main power (v) 3.5v to 60v load 3.5v to 60v 1a continous max v in v cc fault timer inp sns + 0 sns ? bst tgup tgdn ts LTC7003 v cc uv gnd off on iset 10 imon ovlo run 20 30
21 for more information www.linear.com/LTC7003 typical applications 0.1f 7003 ta04a 0.005 bsc047n08ns3 load 3.5v to 48v 10a continuous max v in 3.5v to 48v (60v tolerant) 100k 150k gnd ovlo fault v cc timer 1f 1nf 464k 12.1k sns + sns ? tgup tgdn v in run inp bst ts i set i mon v ccuv on off 0.1f sns + sns ? tgup tgdn v in inp imon iset run 7003 ta05a 0.04 bsc047n08ns3 load 3.5v to 60v 0.5a continuous v in 3.5v to 60v 100k r timer gnd v cc fault timer 1f 10nf bst ts on off v ccuv ovlo v in = 12v v inp = 4v v in = 12v v inp = 4v high side switch with input overvoltage and overcurrent protection high side switch with overcurrent protection and fault latchoff lt c7003 7003f 1a/div v load 10v/div v timer 1a/div 7003 ta05b 12/100ms load pulse r timer = 100k 100ms/div r load LTC7003 10k/div i load 1a/div v load 10v/div v timer 1v/div 7003 ta05c LTC7003 12/100ms load pulse r timer = open 100ms/div r load 10k/div i load
22 for more information www.linear.com/LTC7003 typical applications average current trip 0.1f 0.1f 2 18 5 4 3 7 6 sns + sns ? tgup tgdn v in run inp 7003 ta06a 0.06 si7852adp load 3.5v to 60v <1a average v in 3.5v to 60v 100k + ? + ? + ? 1.2v 1f rb d q 500k ampout 400k 150k 3.3v 3.3v v inp gnd fault v cc v ccuv timer ovlo 1f bst ts i mon i set v in = 12v 4.7f 0.47f load 15mf 7v to 30v 100nf 1f 47f + 1f sns + sns ? tgup tgdn bst ts i mon i set run v in v cc v ccuv fault ovlo inp timer 7003 ta07 0.003 ipb020n10n5 v in 7v to 30v (60v tolerant) 12.1k 294k 100k 220k 10 bas30 gnd on off high side switch with auto-retry, inrush control and ovlo turn-on response lt c7003 7003f v ampout 2v/div v load 10v/div 7003 ta06b LTC7003 v in = 24v 100ms/div LTC7003 v inp 5v/div v load 10v/div i load 1a/div 7003 ta07b ltc1541 response to 1.2a load step 250ms/div i load 1a/div v imon 1v/div
23 for more information www.linear.com/LTC7003 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) package description please refer to http://www.linear.com/product/LTC7003#packaging for the most recent package drawings. lt c7003 7003f
24 for more information www.linear.com/LTC7003 lt 0617 ? printed in usa www.linear.com/LTC7003 ? linear technology corporation 2017 related parts typical application part number description comments ltc7000/ltc7000-1 fast 150v protected high side nmos static switch driver 3.5v to 150v operation, short circuit protected, delta v sns = 30mv, i q = 35a, turn-on (c l = 1 nf) = 35ns, internal charge pump ltc7001 fast 150v high side nmos static switch driver 3.5v to 150v operation, i q ?=?35a, turn-on (c l ?=?1nf)?=?35ns, internal charge?pump ltc7004 fast 60v high side nmos static switch driver 3.5v to 60v operation, i q = 27a, turn-on (c l =1 nf) = 35ns, internal charge pump ltc4440/ltc4440-5/ ltc4440a-5 high speed, high voltage high side gate driver up to 100v supply v oltage, 8v v cc 15v, 2.4a peak pull-up/1.5 peak pull-down ltc7138 high efficiency, 150v 250ma/400ma synchronous step-down regulator integrated power mosfets, 4v v in 150v, 0.8v v out v in , i q ?=?12a, msop-16 (12) ltc7103 105v, 2.3a low emi synchronous step-down regulator 4.4v v in 105v, 1v v out v in , i q ?=?2a fixed frequency 200khz to 2mhz, 5mm x 6mm qfn ltc7801 150v low i q , synchronous step-down dc/dc controller 4v v in 140v, 150v abs max, 0.8v v out 60v, i q ?=?40a ,pll fixed frequency 320khz to 2.25mhz lt1910 protected high side mosfet driver 8v to 48v operation, v sns ?=?65mv, i q ?=?110a, turn-on (c l ?=?1nf)?=?220s, internal charge pump ltc1255 dual 24v high side mosfet driver 9v to 24v operation, v sns ?=?100mv, i q ?=?600a, turn-on (c l ?=?1nf)?=?100s, internal charge pump ltc4367 100v overvoltage, undervoltage and reverse supply protection controller wide operating range: 2.5v to 60v, protection range: C40v to 100v, no tvs required for most applications ltc4368 100v overvoltage, undervoltage and reverse supply protection controller with bidirectional circuit breaker wide operating range: 2.5v to 60v, protection range: C40v to 100v, no tvs required for most applications ltc4364 surge stopper with ideal diode 4v to 80v operation, v sns ?=?50mv, i q ?=?425a, turn-on (c l ?=?1nf)?=?500s, internal charge pump ltc7860 high efficiency switching surge stopper 4v to 60v operation, v sns ?=?95mv, i q ?=?370a, pmos driver ltc4231 micropower hot swap controller 2.7v to 36v operation, v sns ?=?50mv, i q ?=?4a, turn-on (c l ?=?1nf)?=?1ms, internal charge pump ltc3895 150v low i q , synchronous step-down dc/dc controller pll fixed frequency 50khz to 900khz, 4v v in 140v, 0.8v??v out ??60v, i q ?=?40a ltc4380 low quiescent current surge stopper 4v to 80v operation, v sns ?=?50mv, i q ?=?8a, turn-on?=?5ms, internal charge pump ltc3639 high efficiency, 150v 100ma synchronous step-down regulator integrated power mosfets, 4v v in 150v, 0.8v??v out ??v in , i q ?=?12a, msop-16(12) 0.1f 1f vs-12cwq06fn 48v, 500w motor bas116l 7003 ta08 0.004 bsc076n06ns3 load 40v to 60v 8a continuous max v in 40v to 60v 100k m gnd ovlo timer i set v ccuv inp i mon 1nf 100k 86.6k 590k 6.04k 12.1k sns + sns ? tgup tgdn v in run ts bst v cc fault pwm ?20khz protected motor driver lt c7003 7003f LTC7003

▲Up To Search▲

Price & Availability of LTC7003

	To Download LTC7003 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .